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DATA SHEET
128M bits DDR SDRAM
EDD1232AABH (4M words x 32 bits)
Description
The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words x 32 bits x 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 144-ball FBGA package.
Features
* Power supply: VDDQ = 2.5V 0.2V : VDD = 2.5V 0.2V * Data rate: 333Mbps/266Mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * 4 internal banks for concurrent operation * DQS is edge aligned with data for READs; center aligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Data mask (DM) for write data * Auto precharge option for each burst access * SSTL_2 compatible I/O * Programmable burst length (BL): 2, 4, 8 * Programmable /CAS latency (CL): 2, 2.5, 3 * Programmable output driver strength: half/weak * Refresh cycles: 4096 refresh cycles/32ms 7.8s maximum average periodic refresh interval * 2 variations of refresh Auto refresh Self refresh * FBGA package with lead free solder (Sn-Ag-Cu) RoHS compliant
Document No. E0533E50 (Ver. 5.0) Date Published June 2005 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2004-2005
EDD1232AABH
Ordering Information
Part number EDD1232AABH-6B-E EDD1232AABH-7A-E Mask version A Organization (words x bits) 4M x 32 Internal banks 4 Data Rate Mbps (max.) 333 266 JEDEC speed bin (CL-tRCDRD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) Package 144-ball FBGA
Part Number
E D D 12 32 A A BH - 6B - E
Elpida Memory Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank 12: 128M / 4-bank Organization 32: x32 Power Supply, Interface A: 2.5V, SSTL_2 Die Rev. Package BH: FBGA Speed 6B: DDR333B (2.5-3-3) 7A: DDR266A (2-3-3)
Environment Code E: Lead Free
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Pin Configurations
/xxx indicates active low signal.
144-ball FBGA
1 2 3 4 5 6 7 8 9 10 11 12
A B
DQS0
DQ4
DM0 VSSQ
DQ3
VDDQ
DQ2
DQ1
DQ0
DQ31 DQ29 DQ28 VSSQ
NC
DM3
DQS3
VDDQ
DQ5
NC
VDDQ VDDQ DQ30 VDDQ
VDD
VDD
VSS
VSS
VDDQ DQ27
C D E F G H J K L M
DQ6
DQ7
VSSQ VSSQ VSSQ
VSS
VSSQ
VSS
VSSQ VSSQ VSSQ DQ26 DQ25
VSSQ
VSS
VDDQ VDD
VSS
VSS
VSS
VDD
VDDQ DQ24
DQ17 DQ16 VDDQ VSSQ
DQ19 DQ18 VDDQ VSSQ
DQS2 DM2
NC
VSSQ
Thermal Thermal Thermal Thermal
VSSQ VDDQ DQ15 DQ14
Thermal Thermal Thermal Thermal
VSS
VSS
VSS
VSS
VSSQ VDDQ DQ13 DQ12
Thermal Thermal Thermal Thermal
VSS
VSS VSS
VSS
VSS VSS
VSSQ
NC
DM1
DQS1 DQ10
DQ8
NC
DQ21 DQ20 VDDQ VSSQ
Thermal Thermal Thermal Thermal
VSS
VSS
VSSQ VDDQ DQ11
VSSQ VDDQ
VSS
RFU
DQ22 DQ23 VDDQ VSSQ
/CAS
/RAS
VSS
VSS
VDD
A11
VSS
VSS
DQ9
/WE
NC
VDD
NC
VSS
BA1
A10
A2
VDD
A9
RFU
A5
VDD
CK
A8 (AP)
NC
/CK
MCL
/CS
NC
BA0
A0
A1
A3
A4
A6
A7
CKE
VREF
(Top view)
Pin name A0 to A11 BA0, BA1 DQ0 to DQ31 DQS0 to DQS3 /CS /RAS /CAS /WE DM0 to DM3 NC
Function Address inputs Bank select address Data-input/output Input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask No connection
Pin name CK /CK CKE VREF VDD VSS VDDQ VSSQ MCL RFU*
Function Clock input Differential Clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit Must be connected with VSS Reserved for future use
Note: Don't connect.
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................11 Pin Function.................................................................................................................................................12 Command Operation ...................................................................................................................................14 Simplified State Diagram .............................................................................................................................21 Operation of the DDR SDRAM ....................................................................................................................22 Timing Waveforms.......................................................................................................................................41 Package Drawing ........................................................................................................................................47 Recommended Soldering Conditions..........................................................................................................48
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 200 s and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD IOS PD TA Tstg Rating -1.0 to +3.6 -1.0 to +3.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to +70C)
Parameter Supply voltage Symbol VDD, VDDQ VSS, VSSQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VIX (DC) VID (DC) min. 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.5 x VDDQ - 0.2V 0.36 typ. 2.5 0 0.50 x VDDQ VREF -- -- -- 0.5 x VDDQ -- max. 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 Unit V V V V V V V 2 3 4 Notes 1
Input reference voltage Termination voltage Input high voltage Input low voltage Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs
0.5 x VDDQ + 0.2V V VDDQ + 0.6 V 5, 6
Notes: 1. 2. 3. 4. 5. 6.
VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF - 0.18V if measurement.
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
DC Characteristics 1 (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS, VSSQ = 0V)
Parameter Symbol Grade max. 120 160 20 40 35 30 100 -6B -7A -6B -7A 330 260 330 260 200 3 -6B -7A 380 375 Unit mA mA mA mA mA mA mA mA mA mA mA mA Test condition CKE VIH, tRC = tRC (min.) CKE VIH, BL = 4,CL = 2.5, tRC = tRC (min.) CKE VIL CKE VIH, /CS VIH DQ, DQS, DM = VREF CKE VIH, /CS VIH DQ, DQS, DM = VREF CKE VIL CKE VIH, /CS VIH tRAS = tRAS (max.) CKE VIH, BL = 2, CL = 2.5 CKE VIH, BL = 2,CL = 2.5 tRFC = tRFC (min.), Input VIL or VIH Input VDD - 0.2 V Input 0.2 V BL = 4 1, 5, 6, 7 Notes 1, 2, 9 1, 2, 5 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
Operating current (ACT-PRE) IDD0 Operating current (ACT-READ-PRE) Idle power down standby current IDD1 IDD2P
Floating idle standby current IDD2F Quiet idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto Refresh current Self refresh current Operating current (4 banks interleaving) IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A
Notes: 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one clock cycle. 6. DQ, DM and DQS transition twice per one clock cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycle. 10. Command/Address stable at VIH or VIL. DC Characteristics 2 (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS, VSSQ = 0V)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol ILI ILO IOH IOL min. -2 -5 -15.2 15.2 max. 2 5 -- -- Unit A A mA mA Test condition VDD VIN VSS VDDQ VOUT VSS VOUT = 1.95V VOUT = 0.35V Notes
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Pin Capacitance (TA = +25C, VDD, VDDQ = 2.5V 0.2V)
Parameter Input capacitance Symbol CI1 CI2 Data input/output capacitance CI/O Pins CK, /CK All other input pins DQ, DM, DQS min. 1 1 1 typ. -- -- -- max. 5 4 6.5 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. These parameters are measured on conditions: TA = +25C. 2. DOUT circuits are disabled.
f = 100MHz, VOUT = VDDQ/2, VOUT = 0.2V,
AC Characteristics (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS, VSSQ = 0V)
-6B Parameter Clock cycle time (CL = 2) (CL = 2.5) (CL = 3) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS output access time from CK, /CK DQS to DQ skew DQ/DQS output hold time from DQS Symbol tCK tCK tCK tCH tCL tHP tAC tDQSCK tDQSQ tQH min. 7.5 6 6 0.45 0.45 min (tCH, tCL) -0.7 -0.7 -- tHP - 0.55 -- -0.7 0.9 0.4 0.45 0.45 1.75 0 0.25 0.4 0.75 0.2 0.2 0.35 0.35 1.0 1.0 2.2 2 42 60 -- -- -- -- 120000 -- max. 12 12 12 0.55 0.55 -- 0.7 0.7 0.45 -- 0.7 0.7 1.1 0.6 -- -- -- -- -- 0.6 1.25 -- -- -- -7A min. 7.5 7.5 7.5 0.45 0.45 min (tCH, tCL) -0.75 -0.75 -- tHP - 0.75 -- -0.75 0.9 0.4 0.5 0.5 1.75 0 0.25 0.4 0.75 0.2 0.2 0.35 0.35 1.0 1.0 2.2 2 45 67.5 max. 12 12 12 0.55 0.55 -- 0.75 0.75 0.5 -- 0.75 0.75 1.1 0.6 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- -- -- 120000 -- Unit ns ns ns tCK tCK tCK ns ns ns ns ns ns tCK tCK ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK ns ns 8 8 7 9 8 8 7 5, 11 6, 11 2, 11 2, 11 3 Notes 10
Data-out high-impedance time from CK, /CK tHZ Data-out low-impedance time from CK, /CK Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Write preamble setup time Write preamble hold time Write postamble Write command to first DQS latching transition DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input high pulse width DQS input low pulse width Address and control input setup time Address and control input hold time Address and control input pulse width Mode register set command cycle time Active to Precharge command period Active to Active/Auto refresh command period tLZ tRPRE tRPST tDS tDH tDIPW tWPRES tWPREH tWPST tDQSS tDSS tDSH tDQSH tDQSL tIS tIH tIPW tMRD tRAS tRC
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
-6B Parameter Symbol min. 72 18 12 18 max. -- -- -- -- -7A min. 75 20 15 20 max. -- -- -- -- Unit ns ns ns ns ns ns ns tCK tCK s Notes
Auto refresh to Active/Auto refresh command tRFC period Active to Read delay Active to Write delay Precharge to active command period Active to Autoprecharge delay Active to active command period Write recovery time Auto precharge write recovery and precharge time Internal write to Read command delay Average periodic refresh interval tRCDRD tRCDWR tRP tRAP tRRD tWR tDAL tWTR tREF
tRCDRD min. -- 12 18 6 2 -- -- -- -- -- 7.8
tRCDRD min. -- 15 20 6 2 -- -- -- -- -- 7.8
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see `Timing Waveforms' section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle.
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Test Conditions
Parameter Input reference voltage Termination voltage Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate Symbol VREF VTT VIH (AC) VIL (AC) VID (AC) VIX (AC) SLEW Value VDDQ/2 VREF VREF + 0.31 VREF - 0.31 0.62 VREF 1 Unit V V V V V V V/ns
tCK
VDD
CK VID /CK
tCL tCH VIX
VREF
VSS
VDD VIH VIL
t
VREF VSS
SLEW = (VIH (AC) - VIL (AC))/t
VTT
Measurement point
DQ CL = 30pF RT = 50
Input Waveforms and Output Load
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Timing Parameter Measured in Clock Cycle
Number of clock cycle tCK Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 2) (CL = 2.5) (CL = 3) Burst stop command to DQ High-Z (CL = 2) (CL = 2.5) (CL = 3) Read command to write command delay (to output all data) (CL = 2) (CL = 2.5) (CL = 3) Pre-charge command to High-Z (CL = 2) (CL = 2.5) (CL = 3) Write command to data in latency Write recovery time DM to data in latency Mode register set command cycle time Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTW tBSTZ tBSTZ tBSTZ tRWD tRWD tRWD tHZP tHZP tHZP tWCD tWR tDMD tMRD tSNR tSRD tPDEN tPDEX 6ns min. 4 + BL/2 BL/2 3 + BL/2 3 3 2.5 3 3 + BL/2 3 + BL/2 2.5 3 1 3 0 2 12 200 1 1 max. 2.5 3 2.5 3 1 0 1 7.5ns min. 3 + BL/2 BL/2 3 + BL/2 2 3 3 2 2.5 3 2 + BL/2 3 + BL/2 3 + BL/2 2 2.5 3 1 3 0 2 10 200 1 1 max. 2 2.5 3 2 2.5 3 1 0 1 Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Block Diagram
CK /CK CKE
Clock generator
Bank 3 Bank 2 Bank 1
A0 to A11, BA0, BA1
Mode register
Row address buffer and refresh counter
Row decoder
Memory cell array Bank 0
Sense amp.
Command decoder
/CS /RAS /CAS /WE
Column address buffer and burst counter
Column decoder
Control logic
Data control circuit
Latch circuit
DQS
CK, /CK
DLL
Input & Output buffer
DM
DQ
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Pin Function
CK, /CK (input pins) The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /CS (input pin) When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A11 (input pins) Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CK rising edge and the /CK falling edge in a bank active command cycle. Column address (See "Address Pins Table") is loaded via the A0 to the A7 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This column address becomes the starting address of a burst operation. [Address Pins Table]
Address (A0 to A11) Part number EDD1232AABH Row address AX0 to AX11 Column address AY0 to AY7
A8 (AP) (input pin) A8 defines the precharge mode when a precharge command, a read command or a write command is issued. If A8 = High when a precharge command is issued, all banks are precharged. If A8 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A8 = High when read or write command, autoprecharge function is enabled. While A8 = Low, auto-precharge function is disabled. BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL.
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
CKE (input pin) This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or write access. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold time tIH. DM0 to DM3 (input pin) DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS and VREF. When DM = High, the data input at the same timing are masked while the internal burst counter will be counting up. Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table). DQ0 to DQ31 (input/output pins) Data is input to and output from these pins. DQS0 to DQS3 (input and output pin): DQS0 to DQS3 provide the read data strobes (as output) and the write data strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table). [DQS and DM Correspondence Table]
DQS DQS0 DQS1 DQS2 DQS3 Data mask DM0 DM1 DM2 DM3 DQs DQ0 to DQ7 DQ8 to DQ15 DQ16 to DQ23 DQ24 to DQ31
VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. MCL (input pins) This pin must be connected with VSS. operation.
A connection with any level other than VSS may result in undefined
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Command Operation
Command Truth Table DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other combinations than those in the table below are illegal.
CKE Command Ignore command No operation Burst stop in read command Column address and read command Read with auto-precharge Column address and write command Write with auto-precharge Row address strobe and bank active Precharge select bank Precharge all bank Refresh Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL REF SELF Mode register set MRS EMRS n-1 H H H H H H H H H H H H H H n H H H H H H H H H H H L H H /CS H L L L L L L L L L L L L L /RAS /CAS /WE x H H H H H H L L L L L L L x H H L L L L H H H L L L L x H L H H L L H L L H H L L BA1 x x x V V V V V V x x x L L BA0 x x x V V V V V V x x x L H AP x x x L H L H V L H x x L L Address x x x V V V V V x x x x V V
Remark: H: VIH. L: VIL. x: VIH or VIL V: Valid address input Note: The CKE level must be kept for 1 CK cycle at least. Ignore command [DESL] When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal status is held. No operation [NOP] As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data input are neglected and internal status is held. Burst stop in read operation [BST] This command stops a burst read operation, which is not applicable for a burst write operation. Column address strobe and read command [READ] This command starts a read operation. The start address of the burst read is determined by the column address (See "Address Pins Table" in Pin Function) and the bank select address. After the completion of the read operation, the output buffer becomes High-Z. Read with auto-precharge [READA] This command starts a read operation. After completion of the read operation, precharge is automatically executed. Column address strobe and write command [WRIT] This command starts a write operation. The start address of the burst write is determined by the column address (See "Address Pins Table" in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX11). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. Precharge all banks [PALL] This command starts a precharge operation for all banks. Refresh [REF/SELF] This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is self-refresh. For details, refer to the CKE truth table section. Mode register set/Extended mode register set [MRS/EMRS] The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins (the A0 to the A11, BA0 to BA1) in the mode register set cycle. For details, refer to "Mode register and extended mode register set".
CKE Truth Table
CKE Current state Idle Idle Idle Command Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry (PDEN) n-1 H H H H Self refresh Self refresh exit (SELFX) L L Power down Power down exit (PDEX) L L n H L L L H H H H /CS L L L H L H L H /RAS L L H x H x H x /CAS L L H x H x H x /WE H H H x H x H x Address x x x x x x x x Notes 2 2
Remark: H: VIH. L: VIL. x: VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least.
Data Sheet E0533E50 (Ver. 5.0)
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EDD1232AABH
Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM.
Current state Precharging*
1
/CS H L L L L L L L
/RAS /CAS x H H H H L L L x H H H H L L L L x H H H L x H H H H L L L x H H H H L L L x H H L L H H L x H H L L H H L L x H H L x x H H L L H H L x H H L L H H L
/WE x H L H L H L x x H L H L H L H L x H L x x x H L H L H L x x H L H L H L x
Address x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x MODE x x x x x x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* NOP ILLEGAL
11 11 11 11
Next state ldle ldle -- -- -- -- ldle -- ldle ldle
11 11 11
Idle*
2
H L L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST
NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* Activating NOP Refresh/ 12 Self refresh* Mode register set* NOP NOP ILLEGAL ILLEGAL ILLEGAL
12
-- -- -- Active ldle ldle/ Self refresh ldle ldle ldle -- -- -- Active Active
Refresh 3 (auto-refresh)*
H L L L L
Activating*
4
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
11 11 11 11 11
-- -- -- -- -- -- Active Active Active
Active*
5
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL
Starting read operation Read/READA Write Starting write operation recovering/ precharging ILLEGAL*
11
-- Idle --
Pre-charge ILLEGAL
Data Sheet E0533E50 (Ver. 5.0)
16
EDD1232AABH
Current state Read*
6
/CS H L L L L L L L
/RAS /CAS x H H H H L L L x H H H H L L L x H H H x H H L L H H L x H H L L H H L x H H L
/WE x H L H L H L x x H L H L H L x x H L H
Address x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x x x x BA, CA, A8
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP BST Interrupting burst read operation to start new read ILLEGAL* ILLEGAL*
13 11
Next state Active Active Active Active -- -- Precharging -- Precharging Precharging --
14 14 11, 14 11, 14
Interrupting burst read operation to start pre-charge ILLEGAL
Read with auto-preH 7 charge* L L L L L L L Write*
8
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
-- -- -- -- -- Write recovering Write recovering -- Read/ReadA
H L L L
DESL NOP BST READ/READA
NOP NOP ILLEGAL Interrupting burst write operation to start read operation. Interrupting burst write operation to start new write operation. ILLEGAL*
11
L L L L Write recovering*
9
H L L L x H H H H L L L
L H H L x H H L L H H L
L H L x x H L H L H L x
BA, CA, A8 BA, RA BA, A8 x x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x
WRIT/WRITA ACT PRE, PALL
Write/WriteA -- Idle -- Active Active --
Interrupting write operation to start precharge. ILLEGAL NOP NOP ILLEGAL Starting new write operation. ILLEGAL* ILLEGAL* ILLEGAL
11 11
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL
Starting read operation. Read/ReadA Write/WriteA -- -- --
Data Sheet E0533E50 (Ver. 5.0)
17
EDD1232AABH
Current state Write with auto10 pre-charge*
/CS H L L L L L L L
/RAS /CAS x H H H H L L L x H H L L H H L
/WE x H L H L H L x
Address x x x BA, CA, A8 BA, CA, A8 BA, RA BA, A8 x
Command DESL NOP BST READ/READA WRIT/WRIT A ACT PRE, PALL
Operation NOP NOP ILLEGAL ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
14 14 11, 14 11, 14
Next state Precharging Precharging -- -- -- -- -- --
Remark: Notes: 1. 2. 3. 4. 5. 6.
H: VIH. L: VIL. x: VIH or VIL The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. The DDR SDRAM is in "Activating" state for tRCDRD or tRCDWR after ACT command is issued. The DDR SDRAM is in "Active" state after "Activating" is completed. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 11. This command may be issued for other banks, depending on the state of the banks. 12. All banks must be in "IDLE". 13. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.) The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below.
From command Read w/AP
To command (different bank, noninterrupting command) Read or Read w/AP Write or Write w/AP Precharge or Activate
Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/2) 1 1 + (BL/2) + tWTR BL/2 1
Units tCK tCK tCK tCK tCK tCK
Write w/AP
Read or Read w/AP Write or Write w/AP Precharge or Activate
Data Sheet E0533E50 (Ver. 5.0)
18
EDD1232AABH
Command Truth Table for CKE
Current State CKE n-1 n Self refresh H L L L L L Self refresh recovery H H H H H H H H Power down H L L L All banks idle H H H H H H H H H H L Row active H L x H H H H L H H H H L L L L x H H L H H H H H L L L L L x x x /CS x H L L L x H L L L H L L L x H L x H L L L L H L L L L x x x /RAS /CAS /WE Address x x H H L x x H H L x H H L x x H x x H L L L x H L L L x x x x x H L x x x H L x x H L x x x H x x x H L L x x H L L x x x x x x x x x x x x x x x x x x x H x x x x H L x x x H L x x x x x x x x x x x Maintain power down mode Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table CBR (auto) refresh x x x x x x x x x x x x x x Operation INVALID, CK (n-1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CK (n - 1) would exit power down EXIT power down Idle Notes
OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table Self refresh 1
OPCODE Refer to operations in Function Truth Table Power down Refer to operations in Function Truth Table Power down 1 1
Remark: H: VIH. L: VIL. x: VIH or VIL Note: Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state.
Data Sheet E0533E50 (Ver. 5.0)
19
EDD1232AABH
Auto-refresh command [REF] This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The average refresh cycle is 7.8 s. The output buffer becomes High-Z after autorefresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-refresh command. Self-refresh entry [SELF] This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the selfrefresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is terminated by a self-refresh exit command. Power down mode entry [PDEN] tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not disable DLL. Self-refresh exit [SELFX] This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied. ((tSNR =)10 cycles for tCK = 7.5 ns or 12 cycles for tCK = 6.0 ns after [SELFX]) To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Data Sheet E0533E50 (Ver. 5.0)
20
EDD1232AABH
Simplified State Diagram
SELF REFRESH
SR ENTRY SR EXIT
MRS EMRS
MRS
REFRESH
IDLE
*1 AUTO REFRESH
CKE CKE_
ACTIVE CKE_ CKE
ACTIVE POWER DOWN
IDLE POWER DOWN
ROW ACTIVE
BST READ
WRITE
Write
WRITE WITH AP
WRITE
READ WITH AP
READ
Read
READ READ WITH AP
WRITE WITH AP
READ WITH AP
PRECHARGE
WRITEA
PRECHARGE PRECHARGE
READA
POWER APPLIED
POWER ON
PRECHARGE
PRECHARGE
Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
Data Sheet E0533E50 (Ver. 5.0)
21
EDD1232AABH
Operation of the DDR SDRAM
Power-up Sequence (1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200s. (3) After the minimum 200s of stable power and clock (CK, /CK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device. (8) Issue 2 or more auto-refresh commands. (9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting the DLL.
(4) (5) (6) (7) (8) (9)
/CK CK
Command
PALL
EMRS
MRS
PALL
REF REF
tRP
tRFC
REF tRFC
MRS
Any command
2 cycles (min.)
2 cycles (min.) 2 cycles (min.)
DLL reset with A8 = High
2 cycles (min.)
DLL enable
Disable DLL reset with A8 = Low
200 cycles (min)
Power-up Sequence after CKE Goes High Mode Register and Extended Mode Register Set There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A11 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A11 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters shown in the table bellow are allowed to input to the registers.
BA0 BA1 A11 A10 0
MRS
A9 0
A8 DR
A7 0
A6
A5
A4
A3 BT
A2
A1 BL
A0
0
0
0
LMODE
A8 DLL Reset A6 A5 A4 CAS Latency 2 010 0 No 1 Yes
A3 Burst Type 0 Sequential 1 Interleave
A2 A1 A0 0 0 0 0 1 1 1 0 1
Burst Length BT=0 BT=1 2 2 4 8 4 8
1 0
1 1
0 1
2.5 3
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
Data Sheet E0533E50 (Ver. 5.0)
22
EDD1232AABH
BA0 1 BA1 A11 A10 A9
A8 0
A7 0
A6 DS
A5 0
A4 0
A3 0
A2 0
A1 DS
A0 DLL
0
0
0
0
EMRS A6 A1 Driver Strength 0 1 1 Weak (25%) 1 Half (50%)
A0 DLL Control 0 DLL Enable 1 DLL Disable
Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0) Burst Operation The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Data Sheet E0533E50 (Ver. 5.0)
23
EDD1232AABH
Read/Write Operations Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCDRD or tRCDWR after the ACT is issued. Read operation The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A11 and BA0, BA1 pins in the cycle when the read command is issued. The data output timing are characterized by CL and tAC. The read burst start CL * tCK + tAC (ns) after the clock rising edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as read postamble.
t0 CK /CK
tRCDRD
t1
t4
t5
t6
t7
t8
t9
Command
NOP
ACT
NOP
READ
NOP
Address
Row
Column
tRPRE
BL = 2 DQS DQ
out0 out1
tRPST
BL = 4
out0 out1 out2 out3
BL = 8
out0 out1 out2 out3 out4 out5 out6 out7
CL = 2 BL: Burst length
Read Operation (Burst Length)
Data Sheet E0533E50 (Ver. 5.0)
24
EDD1232AABH
t0 CK /CK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
READ
NOP
tRPRE
tRPST
DQS CL = 2 DQ
tRPRE tAC,tDQSCK
VTT
out0
out1
out2
out3
tRPST
VTT
DQS CL = 2.5 DQ
tRPRE
VTT
tAC,tDQSCK
out0
out1
out2
out3
VTT
tRPST
DQS CL = 3
tAC,tDQSCK
VTT
DQ
out0
out1
out2
out3
VTT
Read Operation (/CAS Latency) Write operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle when the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPREH prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write postamble.
t0 CK /CK Command
NOP ACT
Row tRCDWR
t1
t4
t4.5
t5
t6
t7
t8
t9
NOP
WRITE
Column
NOP
Address
tWPREH tWPRES
BL = 2 DQS DQ
in0
in1
tWPST
BL = 4
in0
in1
in2
in3
BL = 8
in0
in1
in2
in3
in4
in5
in6
in7 BL: Burst length
Write Operation
Data Sheet E0533E50 (Ver. 5.0)
25
EDD1232AABH
Burst Stop Burst stop command during burst read The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed.
t0 CK /CK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
READ
BST tBSTZ
NOP 2 cycles
DQS CL = 2 DQ
out0 out1
2.5 cycles
tBSTZ
DQS CL = 2.5 DQ
out0
tBSTZ
out1
3 cycles
DQS CL = 3 DQ
out0 out1
CL: /CAS latency
Burst Stop during a Read Operation
Data Sheet E0533E50 (Ver. 5.0)
26
EDD1232AABH
Auto Precharge Read with auto-precharge The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge command does not limit row commands execution for other bank. Refer to `Function truth table and related note(Notes.*14).
CK /CK
tRAP (min) = tRCDRD (min)
tRPD 2 cycles (= BL/2)
tRP (min)
Command
ACT
READA
NOP
ACT
DQS
tAC,tDQSCK
DQ
out0
out1
out2
out3
Note: Internal auto-precharge starts at the timing indicated by "
".
Read with auto-precharge Write with auto-precharge The precharge is automatically performed after completing a burst write operation. The precharge operation is started (BL/ 2 + 4) cycles after WRITA command issued. A column command to the other banks can be issued the next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row commands execution for other bank. Refer to the `Read with Auto-Precharge Enabled, Write with Auto-Precharge Enabled' section. Refer to `Function truth table and related note (Notes.*14).
CK /CK
tRAS (min)
tRCDWR (min)
tRP
NOP
Command
ACT
NOP
WRITA
ACT
BL/2 + 4 cycles
DM
DQS
DQ
in1
in2
in3
".
in4
BL = 4
Note: Internal auto-precharge starts at the timing indicated by "
Burst Write (BL = 4)
Data Sheet E0533E50 (Ver. 5.0)
27
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the consecutive read command Bank address 1. Same
2.
Same
3.
Different
Data Sheet E0533E50 (Ver. 5.0)
; ;;; ;
EDD1232AABH
Row address State Same Operation ACTIVE Different -- Any ACTIVE IDLE The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCDRD after the ACT command, the consecutive read command can be issued. See `A read command to the consecutive precharge interval' section. The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank without interrupting the preceding read operation. tRP after the precharge command, issue the ACT command. tRCDRD after the ACT command, the consecutive read command can be issued.
t0 t3 t4 t5 t6 t7 t8 t9 CK /CK Command
ACT NOP READ READ NOP
Address
Row
Column A Column B
BA
DQ
out out A0 A1
out B0
out B1
out B2
out B3
Column = A Column = B Read Read
Column = A Dout
Column = B Dout
DQS
Bank0 Active
CL = 2 BL = 4 Bank0
READ to READ Command Interval (same ROW address in the same bank)
28
EDD1232AABH
t0 CK /CK Command ACT Row0 NOP ACT Row1 NOP READ READ NOP t1 t2 t3 t4 t5 t6 t7 t8 t9
Address BA
Column A Column B
DQ Column = A Column = B Read Read
out out A0 A1 Bank0 Dout
out out out out B0 B1 B2 B3 Bank3 Dout
DQS Bank0 Active Bank3 Active Bank0 Read Bank3 Read CL = 2 BL = 4
READ to READ Command Interval (different bank)
Data Sheet E0533E50 (Ver. 5.0)
29
A Write command to the consecutive Write command Interval
Destination row of the consecutive write command Bank address 1. Same Row address State Same
2.
Same
3.
Different
CK /CK Command
Address BA
DQ
DQS
Data Sheet E0533E50 (Ver. 5.0)
;;;;;
EDD1232AABH
Operation ACTIVE Different -- Any ACTIVE IDLE The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued. See `A write command to the consecutive precharge interval' section. The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued.
t0 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6
ACT Row NOP WRIT WRIT
NOP
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Column = B Write
Column = A Write
Bank0 Active
BL = 4 Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
30
CK /CK Command
Address BA
DQ
DQS
;;;; ;;
EDD1232AABH
tn+4 tn+5 t0 t1 t2 tn tn+1 tn+2 tn+3
ACT NOP ACT NOP
WRIT
WRIT
NOP
Row0
Row1
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Bank0 Write Bank3 Write
Bank0 Active
Bank3 Active
BL = 4 Bank0, 3
WRITE to WRITE Command Interval (different bank)
Data Sheet E0533E50 (Ver. 5.0)
31
EDD1232AABH
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write command Bank address 1. Same Row address State Same ACTIVE Operation Issue the BST command. tBSTW ( tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued. See `A read command to the consecutive precharge interval' section. Issue the BST command. tBSTW ( tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCDWR after the ACT command, the consecutive write command can be issued.
2.
Same
Different
--
3.
Different
Any
ACTIVE IDLE
t0 CK /CK
t1
t2
t3
t4
t5
t6
t7
t8
Command
READ
BST
NOP tBSTW ( tBSTZ)
WRIT
NOP
DM
tBSTZ (= CL)
DQ
High-Z
out0 out1
in0
in1
in2
in3
DQS
OUTPUT
INPUT
BL = 4 CL = 2
READ to WRITE Command Interval
Data Sheet E0533E50 (Ver. 5.0)
32
EDD1232AABH
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read command Bank address 1. Same Row address State Same ACTIVE Operation To complete the burst operation, the consecutive read command should be performed tWRD (= BL/ 2 + 3) after the write command. Precharge the bank tWPD after the preceding write command. tRP after the precharge command, issue the ACT command. tRCDRD after the ACT command, the consecutive read command can be issued. See `A read command to the consecutive precharge interval' section. To complete a burst operation, the consecutive read command should be performed tWRD (= BL/ 2 + 3) after the write command. Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCDRD after the ACT command, the consecutive read command can be issued.
2.
Same
Different
--
3.
Different
Any
ACTIVE IDLE
t0
CK /CK
t1
t2
t3
t4
t5
t6
t7
t8
t9
Command
WRIT
NOP
READ
NOP
tWRD (min)
BL/2 + 3 cycle
tWTR*
DM
DQ
in0
in1
in2
in3
out0
out1
out2
out3
DQS
INPUT
OUTPUT
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
BL = 4 CL = 2
WRITE to READ Command Interval
Data Sheet E0533E50 (Ver. 5.0)
33
EDD1232AABH
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read command Bank address 1. 2. 3. Same Same Different Row address State Same Different Any ACTIVE -- ACTIVE IDLE Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. --*
1
DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. --*
1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case. WRITE to READ Command Interval (Same bank, same ROW address)
t0 CK /CK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
READ 1 cycle
NOP
CL=2
DM
DQ
in0
in1
in2
out0 out1 out2 out3
High-Z High-Z
DQS
Data masked
BL = 4 CL= 2
[WRITE to READ delay = 1 clock cycle]
Data Sheet E0533E50 (Ver. 5.0)
34
EDD1232AABH
t0 CK /CK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
NOP 2 cycle
READ CL=2
NOP
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
High-Z High-Z
DQS
Data masked
BL = 4 CL= 2
[WRITE to READ delay = 2 clock cycle]
t0 CK /CK
t1
t2
t3
t4
t5
t6
t7
t8
Command
WRIT
NOP 4 cycle tWTR*
READ CL=2
NOP
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
DQS
Data masked
BL = 4 CL= 2
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 4 clock cycle]
Data Sheet E0533E50 (Ver. 5.0)
35
EDD1232AABH
A Read command to the consecutive Precharge command interval (same bank): To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0 CK /CK Command NOP
READ
t1
t2
t3
t4
t5
t6
t7
t8
NOP
PRE/ PALL
NOP
DQ
out0 out1 out2 out3
DQS tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
t0 CK /CK Command
NOP
t1
t2
t3
t4
t5
t6
t7
t8
READ
NOP
PRE/ PALL
NOP
DQ
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2.5, BL = 4)
t0 CK /CK Command
NOP
t1
t2
t3
t4
t5
t6
t7
t8
READ
NOP
PRE/ PALL
NOP
DQ
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
Data Sheet E0533E50 (Ver. 5.0)
36
EDD1232AABH
READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP (= CL) after the precharge command.
t0 CK /CK Command
NOP READ PRE/PALL NOP High-Z
t1
t2
t3
t4
t5
t6
t7
t8
DQ
out0 out1
DQS
High-Z
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 2, 4, 8)
t0 CK /CK Command
NOP
t1
t2
t3
t4
t5
t6
t7
t8
READ
PRE/PALL CL = 2.5
NOP
High-Z
DQ
out0 out1
High-Z
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2.5, BL = 2, 4, 8)
t0 CK /CK Command
NOP
t1
t2
t3
t4
t5
t6
t7
t8
READ
PRE/PALL CL = 3
NOP
High-Z
DQ
out0 out1
High-Z
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 2, 4, 8)
Data Sheet E0533E50 (Ver. 5.0)
37
A Write command to the consecutive Precharge command interval (same bank) The minimum interval tWPD cycles) is necessary between the write command and the precharge command.
t0 t1 t2 t3 t4 t5 t6 t7
CK /CK Command
DM
DQS
DQ
Precharge Termination in Write Cycles During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command is issued, the invalid data must be masked by DM.
t0 t1 t2 t3 t4 t5 t6 t7
CK /CK Command
DM
DQS
DQ
Data Sheet E0533E50 (Ver. 5.0)
;;;;;;; ;; ;
EDD1232AABH
WRIT NOP PRE/PALL NOP
tWPD
tWR
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
WRIT
NOP
PRE/PALL
NOP
tWR
in0
in1
in2
in3
Data masked
Precharge Termination in Write Cycles (same bank) (BL = 4)
38
EDD1232AABH
Bank active command interval
Destination row of the consecutive ACT command Bank address 1. 2. Same Different Row address Any Any State ACTIVE ACTIVE IDLE Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued. tRRD after an ACT command, the next ACT command can be issued.
CK /CK
Command
ACTV ACT
ACT
NOP
PRE
NOP
ACT
NOP
Address
ROW: 0
ROW: 1
ROW: 0
BA
Bank0 Active Bank3 Active
Bank0 Precharge Bank0 Active
tRRD
tRC
Bank Active to Bank Active Mode register set to Bank-active command interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK /CK Command
MRS NOP ACT NOP
Address
CODE
BS and ROW
Mode Register Set tMRD
Bank3 Active
Data Sheet E0533E50 (Ver. 5.0)
39
EDD1232AABH
DM Control DM can mask input data. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1 t2 t3 t4 t5 t6
DQS
DQ
Mask
Mask
DM
Write mask latency = 0
DM Control
Data Sheet E0533E50 (Ver. 5.0)
40
Timing Waveforms
Command and Addresses Input Timing Definition
CK /CK
Read Timing Definition
/CK CK
DQS
DQ (Dout)
Write Timing Definition
/CK CK
DQS
DQ (Din)
DM
Data Sheet E0533E50 (Ver. 5.0)
;;;;;;
EDD1232AABH
tIS
tIH
Command (/RAS, /CAS, /WE, /CS)
VREF
tIS
tIH
Address
VREF
tCK
tCH
tCL
tDQSCK
tDQSCK
tDQSCK
tDQSCK tRPST
tRPRE
tDQSQ
tLZ
tAC
tQH tAC
tDQSQ
tAC
tQH tHZ
tQH
tDQSQ tQH
tDQSQ
tCK
tDQSS
tDSS
tDSH
tDSS
VREF
tWPRES
tWPREH
tDQSL
tDQSH
tWPST
VREF
tDS
tDH
tDIPW
VREF
tDS
tDH
tDIPW
tDIPW
41
EDD1232AABH
Read Cycle
tCK tCH tCL CK /CK VIH CKE tRAS tRCDRD tIS tIH /CS tIS tIH /RAS tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A8 tIS tIH Address tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRP tRC
DM DQS High-Z tRPRE tRPST
DQ (output)
High-Z Bank 0 Active Bank 0 Read Bank 0 Precharge
CL = 2 BL = 4 Bank0 Access = VIH or VIL
Data Sheet E0533E50 (Ver. 5.0)
42
EDD1232AABH
Write Cycle
tCK tCH CK /CK VIH CKE tRCDWR tIS tIH /CS tIS tIH /RAS tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A8 tIS tIH Address tDQSS DQS (input) tDS DM tDS DQ (input) tWR tDH Bank 0 Active Bank 0 Write Bank 0 Precharge CL = 2 BL = 4 Bank0 Access = VIH or VIL tDH tDQSL tDQSH tDS
tDH
tCL
tRC tRAS tIS tIH tIS tIH tRP tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tWPST
Data Sheet E0533E50 (Ver. 5.0)
43
EDD1232AABH
Mode Register Set Cycle
0
/CK CK CKE /CS /RAS /CAS /WE BA Address DM
High-Z
DQS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VIH
code
valid
code
R: b
C: b
High-Z
DQ (output)
tRP Precharge If needed
tMRD
b
Mode register set
Bank 3 Active
Bank 3 Read
Bank 3 Precharge
CL = 2 BL = 4 = VIH or VIL
Read/Write Cycle
/CK CK CKE /CS /RAS /CAS /WE BA Address
DM
VIH
R:a
C:a
R:b
C:b
C:b''
DQS DQ (output) DQ (input) Bank 0 Active High-Z tRWD Bank 0 Bank 3 Read Active Bank 3 Write
a
b''
b
tWRD Bank 3 Read Read cycle CL = 2 BL = 4 =VIH or VIL
Data Sheet E0533E50 (Ver. 5.0)
44
EDD1232AABH
Auto Refresh Cycle
/CK CK CKE /CS /RAS /CAS /WE BA Address A8=1 R: b C: b VIH
DM DQS DQ (output) High-Z DQ (input) Precharge If needed tRP Auto Refresh tRFC Bank 0 Active Bank 0 Read CL = 2 BL = 4 = VIH or VIL b
Data Sheet E0533E50 (Ver. 5.0)
45
EDD1232AABH
Self Refresh Cycle
/CK CK CKE
tIS
tIH CKE = low
/CS /RAS
/CAS
/WE
BA
Address
A8=1
R: b
C: b
DM DQS DQ (output) High-Z DQ (input) tRP tSNR tSRD Precharge If needed Self refresh entry Self refresh exit Bank 0 Active Bank 0 Read CL = 2.5 BL = 4 = VIH or VIL
Data Sheet E0533E50 (Ver. 5.0)
46
EDD1232AABH
Package Drawing
144-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
0.20 M S B
12.00 0.10
INDEX MARK
0.20
M
SA
12.00 0.10
0.20 S
1.40 max S
0.10 S
0.35 0.05
A
8.80
0.80
INDEX MARK
0.40
0.80
144 - 0.45 0.05 0.15 M S A B 0.08 M S
0.40
8.80
Data Sheet E0533E50 (Ver. 5.0)
B
ECA-TS2-0131-01
47
EDD1232AABH
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD1232AABH. Type of Surface Mount Device EDD1232AABH: 144-ball FBGA < Lead free (Sn-Ag-Cu) >
Data Sheet E0533E50 (Ver. 5.0)
48
EDD1232AABH
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E0533E50 (Ver. 5.0)
49
EDD1232AABH
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0533E50 (Ver. 5.0)
50

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